Akademik Veri Yönetim Sistemi
ARCS 2015 - The 28th International Conference on Architecture of Computing Systems. Proceedings, Porto, Portekiz, 24 - 27 Mart 2015, ss.1-7
This paper applies model checker-based testing, a well-known method from software engineering, to the delay fault testing of synchronous sequential logic circuits. We first model the circuit as timed automata to reveal its timing characteristics. The model is repeatedly mutated by injecting the delay faults under a certain fault assumption and all the mutant models are checked against the given properties by exploiting a model checker. Counterexamples returned from the model checker form the basis of test input sequences. Finally, the test suite minimization is defined as an integer programming problem.