Electrical and Capacitive Behavior of Porous Silicon-Based Au/PS/n-Si Junctions: Influence of Porosity on Charge Transport and Device Performance
SILICON, cilt.03917, ss.1-17, 2026 (SCI-Expanded, Scopus)
- Yayın Türü: Makale / Tam Makale
- Cilt numarası: 03917
- Basım Tarihi: 2026
- Doi Numarası: 10.1007/s12633-026-03917-8
- Dergi Adı: SILICON
- Derginin Tarandığı İndeksler: Scopus, Materials Science & Engineering Collection (ProQuest), Technology Collection (ProQuest), Science Citation Index Expanded (SCI-EXPANDED), Chemical Abstracts Core, Compendex, INSPEC
- Sayfa Sayıları: ss.1-17
- Bursa Uludağ Üniversitesi Adresli: Evet
Özet
Porous silicon (PS) layers were fabricated on Sb-doped n-Si (111) substrates by photo-electrochemical etching using four different HF–dH2O–methanol electrolyte compositions in order to tune porous morphology and interfacial characteristics systematically. The resulting PS layers exhibited porosities of 12.26%–50.18%, pore diameters of 0.2–8.0 μm, and thickness values of 4.46–27.8 μm. Au/PS/n-Si/In junctions demonstrated pronounced rectifying behavior, with rectification ratios at ± 1 V varying from 31.1 to 1957, indicating a strong dependence of diode performance on PS morphology. Electrical characterization reveals ideality factor n = 1.82–3.09, barrier heights of ϕb = 0.80–1.00 eV, and series resistances Rs in the range of 2.04 × 102–1.03 × 104 Ω. These findings suggest that charge transport is governed by morphology-induced barrier inhomogeneity and non-ideal conduction mechanisms within the PS interfacial layer. Optical reflectance measurements indicate an effective band gap between 2.37 and 2.74 eV, which varies with the degree of nanostructuring in the porous network. Frequency-dependent capacitance–voltage (C–V) analysis performed in the 200–1000 kHz range reveals marked dispersion behavior, with apparent barrier heights of 0.48–1.87 eV arising from interface-state and trap-related capacitance contributions. These results demonstrate that electrolyte-controlled PS morphology simultaneously modulates electrical transport, interfacial barrier distribution, and capacitive response in Au/PS/n-Si junctions, providing direct morphology–electrical/ capacitive correlations and practical guidelines for optimizing PS-based device performance.